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智慧財產及商業法院110年度行專訴字第62號

關鍵資訊

  • 裁判案由
    發明專利申請
  • 案件類型
    智財
  • 審判法院
    智慧財產及商業法院
  • 裁判日期
    111 年 08 月 30 日

11062 111810 11010611006307990 1081111 108140830 110510222110525110042271102048730011010611006307990 1 AOI(All area of interest) 2 使 1.121 1 AOI 2 2 12 2.1 AOI 110510ROIregion of interestAOIAOI Areas of interestVarious areas of interest/All area of interest4 AOIAOI2 ROI 3.12246 122461(Field Programmable Gate ArrayFPGA)調 1 112 (Histogram of oriented gradientHOG1HOG2 ROIHOG246 4.133 使3 調調3 3 1AOI2 1.1:An Implementation of the Histogram ofOriented Gradients (HOG) Algorithm on a Reconfigur- able System on ChipHOGHOG 1 1 HOG 1 2.AOI 2HOGsupport vector machineSVM ROI ROI 1 (AOI) 2 2 3.110510ROIAOI1 ROI(region of interest)AOI(area of interest)1ROIAOI ROIAOIAOIareas of interestAll area of interest 4.1 調1 1 1.1HOG1 (HOG) ZedboardXilinx Zynq®-7000All Pro-grammableARM-A9FPGA使CPUFPGA ARM FPGA implementation38410VGA640X4801使 HOG FPGAHOG1HOG 1 2.IC1HOG1534-48HOGFPGA 3. 1 ()111 (AOI) 2HOGSVM ROI 12HOGSVM217.1 3 調調3 ()33調4-9228調133 調311 133 1081111 1098121105101105251115460 11117110851108111 221 222 使 13227011312 1-24-61 233 123 1. 2.61 (AOI) 1 使() 1 / 1 4 LED LEDGPIO 1 1.11076Katsaros NikolaosUniversity of The-ssalyAn Implementation of the Histogram of Oriented Gradients (HOG) Algorithm on a Reconfigura-ble System on Chip1 (1081111)1(Histogram of Oriented GradientsHOG)Xilinx Zynq®-7000Zedboard ARM-A9FPGACPUFPGA 2.2106326HOGSVM2(1081111)2HOGSVMHOG SVM 3.399810US7773145B2AUTOFOCUS UNIT AND CAMERA3(1081111) 3調調 調使便 121 1. FPGA(Field Programmable Gate Array) (Verilog)FPGA FPGA使FPGA HOG(Histogram of Oriented Gradient) HOG HOG 245-246253 SVM(Support Vector Machine) 使SVM便 便SVM SVM 1101 2.1An Implementation of the Histogramof Oriented Gradients (HOG) Algorithm on a Reconfigu-rable System On Chip1achieves real time pedestrian detection at 10VGA images per second with very small decrease in detection accura-cy10VGA 179-801 1254.2 RGB to Grayscale4.2 RGB images require 3 times the resources that grayscale ones do.Due to those reaso ns we decided to transition from RGB images to grayscale ones3 172 1567.1FPGAFrame Grabber Image Preprocessing HOGHOG164117.1使HOGSVM11HOGSVM 3.2569Step1.Step2.Step3.ROI 8*8196198使 5(b)293.42569 1 4.256(a)-(e)( (e))7(ROI)73.2HOG 1961971 (AOI) 5.2103.7HOG 362127x157x15x36121981991 6.216-19使SVM INRIA Person datasetMIT Pedestrian201-203 1 2SVM1 7.121 12121212使HOGSVM122 HOGSVM1 1 8.1(AOI)1 (AOI) ROIregion of interest AOIarea of interest 83211 US10,839,242B11AOIareas of interest(130-31)AOIAOI 1(AOI)(AOI)(AOI)4AOI111105101 (AOI) (AOI) (AOI) AOIAllarea of interest 1AOI1 2 2 9.1FPGA 調198-991 1 1224-6 1.212 112 使()1254.2 RGB to Grayscale(4.2 ) First of all,RGB images require 3 times the re-sources that grayscale ones do. Although this doesn'timmediately affect the software implementation, when it comes to an FPGA, resources are of the essen-ce. Furthermore, it also comes with a computational cost, since in order to extract the gradient of each pixel, the maximum of the gradient values of each co-lor should be computed. In addition, as shown by Dalal & Triggs moving from RGB to grayscale colors reduces the accuracy only by 1.5% at 10-4 FPPW. Dueto those reasons we decided to transition from RGB images to grayscale ones. 3FPGA Dalal & Triggs 1.5%10-4FPPW 1721 12 2122 2.414 114 150516.2 System Overview(6.2 )Figure 6.1: System Overview(6.1 The image above is an abstract representation of the implemented system on the Zedboard FPGA. As it can be seen, the input is captured from the webcam connected to the FPGA and the outputis projected to a VGA monitor. An embedded applicat-ion is being executed on the Petalinux operating sys-tem running on the processing system of the board. Finally, all the accelerators and the display controller which are implemented on the programmable logicare being controlled from the embedded application. Zedboard FPGA FPGA(Video Graphics ArrayVGA) Petalinux 1656.1E mbedded ApplicationPetalinuxHOG SVM 22HOG SVM194使124 124 3.545 445 LED LEDGPIO LED LEDGPIO 12512 5 4.616 116 218使INRIA Person datasetMIT Pedestrian202 12612 6 1233 313 113 / 3 150516.2 6.12212384-9At step S100, the initial standard area is set based on the first frame of the image data soon after the first switch is switched on. At step S101,the change areais defined with the initial standard area at its cen-ter and the target-imaging area is established. Atstep S102,it is determined whether or not the target-imaging area is within the change area.When the target-imaging area is within the change area, the pro-cess proceeds to step S103. When the target-imagingarea is outside or the change area, the process pro-ceeds to step SI04. At step S103,the same unit areaas the standard area is set as the scanning area. Onthe other hand, at step S104,the target-imaging area is set as the scanning area. After step S103 or S104,the process proceeds to step S105.At step S105,the position of the focus lens is adjusted by repeating the contrast value detection process with associated focus lens movements, based on the image data corres-poding to the scanning area. At step S106,the scann-ing area becomes the new standard area. After sett-ing the standard area, the process proceeds to step S107. At step S107, it is determined whether or not the first switch is switched off. When the firstswi-tch is remains on by keeping the release buttonde-pressed halfway,the process returns to step S101,and the pursuit auto focus function is repeated.However, when the first switch is switched off at step S107, the pursuit auto focus function terminates andthe process for the pursuit auto focus is complete. S100S101S102S103S104S103S104S103S104S105S105調S106S107S107S101S1071543調3 1-3 123 3使12 3 123 31233 123 US10,839,242134 222 1981         111    8     30         202020 24111 12 ()  1. 2. 3. () 1. 2. 3. 4. ()()()         111    9     5