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in判決書

最高行政法院(含改制前行政法院)九十三年度判字第一一○七號

關鍵資訊

  • 裁判案由
    新型專利舉發
  • 案件類型
    行政
  • 審判法院
    最高行政法院(含改制前行政法院)
  • 裁判日期
    93 年 08 月 31 日

                                         11735 IDE IDE IDE ID EIDE DRAMSDRAM IDE 使 IDE IDE 0000000 0000000Int.CIG06F 11/00 G06F 13/14References Cited WTO WIPO調 IDE IDEIDE 00000000滿 西00 00000 Solut ion Guide vol.71西 調 Flash Memory IDE IDE ... These and additional objects are accomplished by improvements in the architecture of a system of EEprom chips, and the circuits and techniques therein. According to one aspect of the present invention, an array of Flash EEprom cells on a chip is organized into sectors such that all cells within each sector are erasable at once. A Flash EEprom memory system comprises one or more Flash EEprom chips under the control of a controller. The invention allows any combination of sectors among the chips to be selected and then erased simultaneously. This is faster and more efficient than prior art schemes where all the sectors must be erased every time or only one sector at a time can be erased.FIG.2 illustrates schematically selected multiple sectors for erase. A Flash EEprom system includes one or more Flash EEprom chips such as 201,203,205. They are in communication with a controller 31 through lines 209. Typically, the controller 31 is itself in communication with a microprocessor systemnot shown. The memory in each Flash EEprom chip is partitioned into sectors where all memory cells within a sector are erasable together. For example, each sector may have 512 bytei.e.512×8 cells available to the user, and a chip may have 1024 sectors. Each sector is individually addressable, and may be selected, such as sectors 211,213,215,217 in a multiple sector erase. As illustrated in FIG.2, the selected sectors may be confined to one EEprom chip or be distributed among several chips in a system. The sectors that were selected will all be erased together. This capability will allow the memory and system of the present invention to operate much faster than the prior art architectures. 使 201203205 20931 31 512512×8 1024 211213215217 使 IDE IDE 使Solid State Process IDE使 0000000 IDE