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臺灣臺北地方法院111年度訴字第4247號

關鍵資訊

  • 裁判案由
    損害賠償等
  • 案件類型
    民事
  • 審判法院
    臺灣臺北地方法院
  • 裁判日期
    113 年 03 月 08 日

  • 當事人
    揚智科技股份有限公司梁厚誼

1114247 駿 11315 8522551121228 112122811256587700209215 2551232291231149312 1125,1725 9172271 2314951 3321971,2873,9775 196 4.1.6 3使 23.1WiFi/ SB/BLE BB/Mac3.24.1.24.1.44.1.6 1108111101013 11115110124.1.6111154.1.3 IC使1,2320,760553,2171,2873,977 22912311111321RF IP 4.1.6 ICIC227123114.1.6 7.2西52437130 493124951 1,2873,9775 Wi-Fi 6 RFWiFi 6 RF CEVA Mac DBBLicensed IP System on a Chip, SOC 4.1.6 13.213.31108231109281101013Multiple Project Wafer, MPW4.1.6 111425AIXLINK 4.1.6 3.1.3III11RF IP 5.28.2使RF IP 調1,1748,805 198199197 109113230 4.14.2 2.4GhzWiFi SB RF/BLE BB/MacASICshuttle engineering sampletape-out 西5243714.1.6 1115241116234147495197100 111154.1.61,2873,97722912311111321IC22712311493124951 229123111,2873,977227123111,2873,9774931249511,2873,977 1083464901 11.1WiFiBB/Mac IP 1.1.121.1.2WiFi SBRF/BLE BB/MacASICAli ICASIC3.11.1.3WiFiDB RF/BLE BB/MacASIC 3.21.24.12.1Single Band RF IP Dual Band RF IP,使使使8 使3.13.1.13.1.2 使Single Band3.1.3I.II. III.IV. Bi-Weekly Review MeetingRF IP Third party IP integration into ASIClayoutreview2223SOCSystem integration; SSI3211.2" "ALi"Licensed Product"means an integrated circuit designed or dveloped by ALi, which contains the Licensed IP under this Agreement. 369391使使Licensed IP使 使使4.1230使4.1.24.1.49981 使使使使 229123111,2873,977 滿229123114.1.2Datain304.1.3 shuttle engineering sampletape-out204.1.6 25滿 4.1.6 196 11115LINE 11115 LINE27127811115 4.1.6 3.1 4.1 4.1.3 shuttleengineering sample tape-out202510ALi is responsible for all tape-outs of ALi's Licensed Products, including MPW and production.359390914.1.3 4.1.3 4.1.6 4.1.6 13.21 Deliverables213.3 3 IP delivery and Deliverables43738 4.1.14.1.64.1.14.1.54.1.64.1.613.34 AIXLINK 249283AIXLINK (1) 3/21ICWiFi250 183189IC使4.1.6 IC使 4.1.6 3033253493511172 4.1.6 1,2873,97722912311 227123114 931249511,287 3,977 4.1.6 13.34 IC使4.1.6 19812022321RF IP4.1.6 39調4.1.6 4.1.6 1,2873,977 229123112271231149312 49511,2873,9775 78         113    3     8    20         113    3     8    79 1 RF calibration 1,103,293 2 AGC 710,516 3 RFD simualtion 603,719 4 RFD review 668,293 5 RF LDO check 613,984 6 RFD verification 156,695 7 RF AD/DA analysis 1,050,096 8 RFA TX power table 1,122,403 9 RFA RX gain table 735,039 10 BLE RF behavior 979,488 11 PCB rework 288,095 12 RF 802,910 13 RF measurement 215,079 14 RF&CEVAreview 1,064,029 15 Lucio RF 452,000 16 RFA AD/DA bug fix 505,024 17 BLE SX bug fix 506,413 18 RF power control fix 743,684 12,320,760 341342 1 Shuttle IC 100 ICFIBFIB 474,887 2 FIB IC FIBICShuttle ICFIB 78,330 553,217 1 RF Macro Verilog Frame and Behavior Model are Ready GDS Frame is ReadyRF IP area shape, pin, and pad locations are determined .lib and .pg.lib are Ready; ESD Power Structure Control plan to EFEM integration Updated link-budget for EFEM Circuits calibration plans for Modem RFIP test planRX, TX, SX, DPD, and ADC/DAC Test-bench delivery and simulation results a. EM files and netlist b. PVT check results c. Updated check list of each design blocks 2 a. Verilog-RN model b. Abstract viewGDS of the IP frame c. .lib, .lef, .def, and .v d. ESD review plan 3 MP Quality RF IP GDS and Final Spice Netlist are Ready 4 a. LVS Pass, DRC Clean,ESD& Latch-Up and Density Clean GDS b. Final LVS netlist c. PAD list d. Control register map e. Documentation for integration guidelines i. Recommended check lists in integrations f. Final AGC plan and gain control2 versions. Wi/o EFEM g. Test-bench delivery and simulation results i. EM files and netlist ii. PVT check resultsPost-simulation, critical blocks iii. Final check list of each design blocks h. Calibration FW