The Export of Goods (Control) (Amendment No 7) Order 1994

Section 1
This Order may be cited as the Export of Goods (Control) (Amendment No 7) Order 1994 and shall come into force on 2nd March 1994.
Section 2
The Export of Goods (Control) Order 1992 shall be further amended as follows:—
in Group 3 of Part III of Schedule 1—
(i) for entry 3A001 sub—head a.2, there shall be substituted the following:
Microprocessor microcircuits, microcomputer microcircuits, microcontroller microcircuits, electrical erasable programmable read-only memories ( EEPROMs ), static random-access memories ( SRAMs ), storage integrated circuits manufactured from a compound semiconductor, analogue-to-digital converters, digital-to-analogue converters, electro-optical or optical integrated circuits for signal processing, field programmable gate arrays, field programmable logic arrays, neural network integrated circuits, custom integrated circuits for which either the function is unknown or the control status of the equipment in which the integrated circuit will be used is unknown, or Fast Fourier Transform ( FFT ) processors, as follows:
Rated for operation at an ambient temperature above 398 K (125°C);
Rated for operation at an ambient temperature below 218 K (−55°C); or
Rated for operation over the entire ambient temperature range from 218 K (−55°C) to 398 K (125°C);
Note: This sub-head does not apply to integrated circuits for civil automobile or railway train applications.
(ii) for entry 3A001 sub-head a.11, there shall be substituted the following:
Digital integrated circuits based upon any compound semiconductor and having either of the following:
An equivalent gate count of more than 300 (2 input gates); or
A toggle frequency exceeding 1.2 GHz .
Note: This sub-head does not apply to microprocessor microcircuits, microcomputer microcircuits, microcontroller microcircuits, electrical erasable programmable read-only memories (EEPROMs), static random-access memories (SRAMs), storage integrated circuits manufactured from a compound semiconductor, analogue-to-digital converters, digital-to- analogue converters, electro-optical or optical integrated circuits for signal processing, field programmable gate arrays, field programmable logic arrays, neural network integrated circuits, custom integrated circuits for which either the function is unknown or the control status of the equipment in which the integrated circuit will be used is unknown, or Fast Fourier Transform (FFT) processors;
(iii) in Note 2.b to entry 4A003, N.B. 1 shall be deleted and in N.B 2, the number “2.” shall be deleted;
(iv) in entry 4A003 head g shall be deleted;
(v) in Category 4, for the Technical Note to Category 4 there shall be substituted the following:
Note to Category 4
Composite Theoretical Performance ( CTP )
Abbreviations used in this Note CE computing element (typically an arithmetic logical unit) FP floating point XP fixed point t execution time XOR exclusive OR CPU central processing unit TP theoretical performance (of a single CE) CTP composite theoretical performance (multiple CEs) R effective calculating rate WL word length L word length adjustment * multiply Execution time ‘t’ is expressed in microseconds, TP and CTP are expressed in millions of theoretical operations per second ( Mtops ) and WL is expressed in bits. Outline of the CTP calculation method CTP is a measure of computational performance given in Mtops. For the purpose of this category, in calculating the CTP of an aggregation of CEs the following three steps are required:
(1) Calculate the effective calculating rate R for each CE;
(2) Apply the word length adjustment (L) to the effective calculating rate (R), resulting in a Theoretical Performance (TP) for each CE;
(3) If there is more than one CE, combine the TPs resulting in a CTP for the aggregation.
Details of these steps follow.
Step 1: The effective calculating rate R
FP only
(R fp ) Max
Both FP and XP
(R) Calculate both
R xp ' R fp
Where t log is the execute time of the XOR, of for logic hardware not implementing the XOR, the fastest simple logic operation.
Where R| is the number of results per second, WL is the number of bits upon which the logic operation occurs, and 64 is a factor to normalise to a 64 bit operation.
For a CE which performs multiple operations of a specific type in a single cycle (e.g., two additions per cycle or two identical logic operations per cycle), the execution time t is given by:
For the CE that does not implement FP add or FP multiply, but that performs FP divide:
Rates should be calculated for all supported operand lengths considering both pipelined operations (if supported), and non-pipelined operations using the fastest executing instruction for each operand length based on:
(1) Pipelined or register-to-register operations. Exclude extraordinarily short execution times generated for operations on a predetermined operand or operands (for example, multiplication by 0 or 1). If no register-to register operations are implemented, continue with (2).
(2) The faster of register-to-memory or memory-to-register operations; if these also do not exist, then continue with (3).
(3) Memory-to-memory.
In each case above, use the shortest execution time certified by the manufacturer.
Step 2: TP for each supported operand length WL
Adjust the effective rate R (or R') by the word length adjustment L as follows:
where L = (1/3 + WL/96)
This adjustment is not applied to specialised logic processors which do not use XOR instructions. In this case TP = R.
Select the maximum resulting value of TP for:
Each XP—only CE (R xp );
Each FP—only CE (R fp );
Each combined FP and XP CE (R);
Each simple logic processor not implementing any of the specified arithmetic operations; and
Each special logic processor not using any of the specified arithmetic or logic operations.
Step 3: CTP for aggregations of CEs, including CPUs
For a CPU with a single CE,
CTP = TP
(for CEs performing both fixed and floating point operations
TP = max (TP fp , TP xp ))
CTP for aggregations of multiple CEs operating simultaneously is calculated as follows:
where the TPs are ordered by value, with TP1 being the highest, TP2 being the second highest,…, and TPn being the lowest. Ci is a coefficient determined by the strength of the interconnection between CEs, as follows:
For multiple CEs operating simultaneously and sharing memory:
C 2 = C 3 = C 4 = … = C n = 0.75
where m = number of CEs or groups of CEs sharing access.
provided:
(1) The TPi of each CE or group of CEs does not exceed 30 Mtops;
(2) The CEs or groups of CEs share access to main memory (excluding cache memory) over a single channel; and
(3) Only one CE or group of CEs can have use of the channel at any given time.
N.B. This does not apply to items controlled under Category 3.
For multiple CEs or groups of CEs not sharing memory, interconnected by one or more data channels:
C i = 0.75 * k i (i = 2, …,32) (see Note below)
= 0.60 * k i (i = 33, …,64)
= 0.45 * k i (i = 65, …,256)
= 0.30 * k i (i > 256)
The value of C i is based on the number of CEs, not the number of nodes.
where
k i = min (S i /K r, 1), and
K r = normalising factor of 20 Mbytes/s.
S i = sum of the maximum data rates (in units of Mbytes/s) for all data channels connected to the i th CE or group of CEs sharing memory.
When calculating a C i for a group of CEs, the number of the first CE in a group determines the proper limit for C i . For example, in an aggregation of groups consisting of 3 CEs each, the 22nd group will contain CE 64 , CE 65 and CE 66 . The proper limit for C i for this group is 0.60.
Aggregation (of CEs or groups of CEs) should be from fastest-to-slowest; i.e.:
TP 1 ≥ TP 2 ≥ … ≥ TP n, and
in the case of TP i = TP i+1 , from the largest to smallest; i.e.:
C i ≥ C i+1
(vi) in entry 5A001 sub-head b.10.b shall be deleted.
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